HUANG, Jiayi - HKUST Class Schedule & Quota

Class Schedule & Quota
2025-26 Fall 2024-25 Summer 2024-25 Spring 2021-22 Winter
2025-26 Fall
Common Core Course
The class information on this page will normally be updated every 15 to 20 minutes during class enrollment period.
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COURSE INFO

VECTOR	[3-0-0:3]
DESCRIPTION	This course aims to build a strong foundation and equip students with insights and techniques in modern microprocessor architecture for future system design. The course covers fundamental and advanced concepts, including processor design, memory hierarchy, pipelining, caching, multicore architectures, GPU, interconnection networks, and domain-specific optimizations. Students will gain a deep understanding of how microprocessors are designed and optimized for performance, efficiency, and scalability, preparing them for challenges in the evolving landscape of computing.

VECTOR

[3-0-0:3]

DESCRIPTION

This course aims to build a strong foundation and equip students with insights and techniques in modern microprocessor architecture for future system design. The course covers fundamental and advanced concepts, including processor design, memory hierarchy, pipelining, caching, multicore architectures, GPU, interconnection networks, and domain-specific optimizations. Students will gain a deep understanding of how microprocessors are designed and optimized for performance, efficiency, and scalability, preparing them for challenges in the evolving landscape of computing.

MICS 6002B - Microprocessor Architecture (3 units)

Section	Date & Time	Room	Instructor	Quota	Enrol	Avail	Wait	Remarks
L01 (6209)	Th 09:00AM - 11:50AM	Rm 201, E3	HUANG, Jiayi	20	5	15	0