LU, Zhonghai - HKUST Class Schedule & Quota

Class Schedule & Quota
2025-26 Fall 2024-25 Summer 2024-25 Spring 2021-22 Winter
2025-26 Fall
Common Core Course
The class information on this page will normally be updated every 15 to 20 minutes during class enrollment period.
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COURSE INFO

VECTOR	[2-1-0:3]
DESCRIPTION	The course focuses on the communication problem of on-chip many-core architectures. It introduces basic concepts and principles of on-chip bus and interconnection network, in particular, about network topology, routing and flow control, deadlock/livelock, and quality-of-service (QoS) et cetera. It presents the micro-architecture details of on-chip router and network interface designs for both message passing and shared memory systems. Furthermore, theoretical and experimental performance evaluation methodology will be investigated.

VECTOR

[2-1-0:3]

DESCRIPTION

The course focuses on the communication problem of on-chip many-core architectures. It introduces basic concepts and principles of on-chip bus and interconnection network, in particular, about network topology, routing and flow control, deadlock/livelock, and quality-of-service (QoS) et cetera. It presents the micro-architecture details of on-chip router and network interface designs for both message passing and shared memory systems. Furthermore, theoretical and experimental performance evaluation methodology will be investigated.

MICS 6002I - Network on Chip (3 units)

Section	Date & Time	Room	Instructor	Quota	Enrol	Avail	Wait	Remarks
L01 (6216)	We 01:30PM - 03:20PM	Rm 202, E1	LU, Zhonghai	30	8	22	0
T01 (6217)	We 03:30PM - 04:20PM	Rm 202, E1	LU, Zhonghai	30	8	22	0